Biography
Aurelio Morales Villanueva is a professor of the Electronics Engineering Department, College of Electrical and Electronics Engineering, at Universidad Nacional de Ingeniería (UNI), Perú. He has experience in presale, after sale and administration of data communication infrastructure projects and computing platforms in transnational companies in the telecommunications sector. His research interests include partial dynamic reconfiguration on FPGAs, computer architecture and embedded SoC on FPGAs, and digital ASIC VLSI design using open-source software tools.
Interests
- Dynamic Reconfiguration on FPGAs
- Parallel/Distributed Computer Architecture
- FPGA-based System on Chip (SoC)
- Digital ASIC VLSI design using open-software tools
Education
PhD in Electrical & Computer Engineering, 2015
University of Florida, U.S.A.
MSc in Electrical Engineering, 1994
State University of New York, Buffalo, U.S.A.
MSc in Electronics Engineering, 1991
Universidad Nacional de Ingeniería, Perú
BSc in Electronics Engineering, 1985
Universidad Nacional de Ingeniería, Perú
Skills
Technical
VHDL language
ANSI C language
Quartus Prime (Altera) & ISE (Xilinx) EDA tools
Hobbies
Comic books
Cats
Photography
Professional Experience
Pre sales engineer
Telefónica del Perú S.A.A.
Data communications pre sales engineer for Poder Judicial, CCFFAA, ONP, FAP, Minedu, SIMA
Senior support engineer
Telefónica Empresas Perú S.A.A.
Support engineer for Sun Microsystems platforms in Telefonica group
Project engineer
Telefónica Sistemas Sucursal del Peru S.A.
Pre sales engineer for computing platforms in Telefonica group
Academic Experience
Professor
Taught electronics engineering courses (undergraduate) and researched on FPGA applications.
Associate Professor
Taught electronics engineering courses (undergraduate and graduate) and researched on FPGA applications.
Assistant Professor
Taught electronics engineering courses (undergraduate).
Projects
*
Project developed at the College of Electrical and Electronics Engineering, Universidad Nacional de Ingeniería (UNI) as part of the Universalization in IC Design by IEEE CAS Society (UNIC-CASS).
Project developed as a graduate research volunteer student at National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC), as part of the doctoral program at the University of Florida.
Project developed as a graduate research volunteer student at National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC), as part of the doctoral program at the University of Florida.
Project developed at the Research Institue of the College of Electrical and Electronics Engineering (IIFIEE) at the Universidad Nacional de Ingeniería (UNI), Perú, before being engaged in a doctoral program at the University of Florida.
Project developed at the Research Institue of the College of Electrical and Electronics Engineering (IIFIEE) at the Universidad Nacional de Ingeniería (UNI), Perú, before being engaged in a doctoral program at the University of Florida. This project was presented at IEEE INTERCON 2011 held at UNI.
Project developed at the Research Institue of the College of Electrical and Electronics Engineering (IIFIEE) at the Universidad Nacional de Ingeniería (UNI), Perú, before being engaged in a doctoral program at the University of Florida.
Journal & Conference Papers
(2024).
Uncertainty Evaluation of a Gas Turbine Model Based on a Nonlinear Autoregressive Exogenous Model and Monte Carlo Dropout.
MDPI Sensors 2024, 24(2), 465.
(2021).
Exploring Dynamic Partial Reconfiguration in a Tightly-coupled Coprocessor Attached to a RISC-V Soft-processor on a FPGA.
In 2021 IEEE XXVIII International Conference on Electronics, Electrical Engineering and Computing (INTERCON).
(2017).
Relocation of Hardware Tasks across Networked Partially Reconfigurable FPGAs.
In 2017 Electronic Congress (E-CON UNI).
(2016).
Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs.
In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition DATE.
(2015).
Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs.
In 2015 IEEE International Parallel and Distributed Processing Symposium Workshop.
Works that reference my research
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(2022).
A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices.
MDPI Electronics 2023, 12(1), 102.
(2022).
A High-Level Synthesis Approach Applicable to Autonomous Embedded Systems.
2022 IEEE XXIX International Conference on Electronics, Electrical Engineering and Computing (INTERCON).
(2021).
A Survey: FPGA-Based Dynamic Scheduling of Hardware Tasks.
Chinese Journal of Electronics Vol.30, No.6, Nov. 2021.
(2020).
Automatic Accelerator Preemption.
Computer Science and Engineering Department, University of Michigan, USA.
(2019).
Context Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs.
2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).
Contact
- amorales@uni.edu.pe
- +51 381 6700
- Av. Túpac Amaru 210, Rimac, Lima 15333
- Friday 10:00 to 13:00