On-Chip Context Save and Restore on Partially Reconfigurable FPGAs

Partial reconfiguration (PR) enables hardware tasks to time multiplex partially reconfigurable regions (PRRs) by isolating reconfiguration to only the reconfigured PRR, which avoids halting the entire FPGA’s execution. Time multiplexing PRRs requires support for unloading/loading hardware tasks and for resuming a task’s execution state. The execution state (context) must be saved when the task is unloaded so that the execution state can be restored when the task resumes — context save (CS) and context restore (CR), respectively. This context save and restore (CSR) process can significantly enhance system functionality by eliminating lengthy re-execution time. CSR has high potential for applications such as dynamic load balancing and task migration between pooled FPGA resources, target tracking where fast moving, critical targets must be continually monitored (e.g., incoming missiles), etc. The CSR tool is C-based and currently supports CLB/BRAM/LUTRAM-based hardware tasks on Xilinx Virtex-5 devices, and can be easily ported to new Xilinx device families.