On-Chip Hardware Task Relocation on Partially Reconfigurable FPGAs

Partial reconfiguration (PR) enables shared FPGA systems to non-intrusively time multiplex hardware tasks in partially reconfigurable regions (PRRs). To fully exploit PR, higher priority tasks should preempt lower priority tasks and preempted tasks should resume execution in any PRR with available resources. This preemption/resumption requires saving/restoring the preempted task’s execution context and relocating the task to another PRR. The on-chip hardware task relocation (HTR) software enables a task’s execution state to be saved, relocated to, and restored in any heterogeneous PRR with sufficient resources. HTR has high potentical for applications such as dynamic load balancing and task migration between pooled FPGA resources in a network of FPGAs, target tracking where fast moving, critical targets must be continually monitored (e.g., incoming missiles), etc. The HTR tool is C-based and currently supports CLB/BRAM/LUTRAM-based hardware tasks on Xilinx Virtex-5 devices, and can be easily ported to new Xilinx device families.