Paper-Conference

A High-Level Synthesis Approach Applicable to Autonomous Embedded Systems

Denis S. Loubach

Exploring Dynamic Partial Reconfiguration in a Tightly-coupled Coprocessor Attached to a RISC-V Soft-processor on a FPGA

Jairo Walber Abdala Castro, Aurelio Morales Villanueva

Automatic Accelerator Preemption

Alireza Khadem, Sai Rohit Kandula

Context Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs

Marcel Eckert, Dominik Meyer, Bernd Klauer

A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA

Tingyu Zhou, Tieyuan Pan, Zhiguo Bao, Takahiro Watanabe

Relocation of Hardware Tasks across Networked Partially Reconfigurable FPGAs

Aurelio Morales Villanueva

CPRtree: A Tree-based Checkpointing Architecture for Heterogeneous FPGA Computing

Hoang-Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima

Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs

Aurelio Morales Villanueva, Rohit Kumar, Ann Gordon-Ross

Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs

Aurelio Morales Villanueva, Ann Gordon-Ross

A Highly Flexible Reconfigurable System on a Xilinx FPGA

Tomáš Drahoňovský, Martin Rozkovec, Ondřej Novák