Aurelio Morales Villanueva
Aurelio Morales Villanueva
Home
Projects
Journal & Conference Papers
Contact
CV
Light
Dark
Automatic
Paper-Conference
A High-Level Synthesis Approach Applicable to Autonomous Embedded Systems
Denis S. Loubach
PDF
DOI
Exploring Dynamic Partial Reconfiguration in a Tightly-coupled Coprocessor Attached to a RISC-V Soft-processor on a FPGA
Jairo Walber Abdala Castro
,
Aurelio Morales Villanueva
PDF
Slides
DOI
Automatic Accelerator Preemption
Alireza Khadem
,
Sai Rohit Kandula
PDF
Project
Context Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs
Marcel Eckert
,
Dominik Meyer
,
Bernd Klauer
PDF
DOI
A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA
Tingyu Zhou
,
Tieyuan Pan
,
Zhiguo Bao
,
Takahiro Watanabe
PDF
DOI
Relocation of Hardware Tasks across Networked Partially Reconfigurable FPGAs
Aurelio Morales Villanueva
PDF
Slides
DOI
CPRtree: A Tree-based Checkpointing Architecture for Heterogeneous FPGA Computing
Hoang-Gia Vu
,
Supasit Kajkamhaeng
,
Shinya Takamaeda-Yamazaki
,
Yasuhiko Nakashima
PDF
DOI
Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs
Aurelio Morales Villanueva
,
Rohit Kumar
,
Ann Gordon-Ross
PDF
Poster
Slides
DOI
Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs
Aurelio Morales Villanueva
,
Ann Gordon-Ross
PDF
Slides
DOI
A Highly Flexible Reconfigurable System on a Xilinx FPGA
Tomáš Drahoňovský
,
Martin Rozkovec
,
Ondřej Novák
PDF
DOI
»
Cite
×