FPGA accelerators are being used for various applications and have found a place in the cloud and mobile devices. By mapping various contexts/tasks to a single FPGA chip to improve the FPGA utilization and sharing. However, FPGAs inherently do not support context switching and it has to be built into the initial RTL files manually, which increases the development time. Our project is to create a framework to automatically add preemption capabilities to any HDL design. We achieve this goal in four stages, being Prepass, in which we preprocess the design, Remove FF, which removes all of the registers from the accelerator, Add State Module that adds a new module named State Module and keeps all of the design states, and Make Top Module in which we introduce a new top module consisting of the previous design and the State Module. To evaluate this idea, we tested on two popular accelerators. First, Neural Network Accelerator processes a fully-connected neural network and reads/stores from/to the off-chip memory using Avalon Memory Mapped interface. Second, Edit Distance Accelerator which is commonly used in Genome Sequencing. We stick to the dynamic programming approach of this algorithm and implement the accelerator in a systolic-array mode. We break the initial body of our testbenches into different contexts and interleave them on the FPGA. Finally, we synthesize our preemptable accelerators using the Vivado Design Suite and found the overhead of State Module to be 34% and 52% on the Neural Network Accelerator and Edit Distance Accelerator, respectively.